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Chip Placement with Deep Reinforcement Learning


Azalia Mirhoseini: So excited to share our work on RL for Chip Placement, which enables chip optimization in < 6 hrs, whereas baselines require manual efforts and can take weeks. Joint work with my co-TL @annadgoldie, @JeffDean (cont.) Paper: Blog:

12 replies, 959 likes

Jeff Dean (@🏡): I'm very excited to point at a new paper on "Chip Placement with Deep Reinforcement Learning" that @Azaliamirh, @annadgoldie and many other co-authors and I put up on Arxiv. Blog: Paper:

9 replies, 480 likes

Google AI: Check out a new deep #ReinforcementLearning approach to hardware accelerator chip design, which rapidly generates chip placements that exhibit competitive performance with their manually designed counterparts. Read more ↓

7 replies, 400 likes

Anna D Goldie: Just released the paper and blog post for Chip Design with Deep Reinforcement Learning! (, Really excited to finally share this work! Thank you to all of my amazing collaborators, especially my co-lead @Azaliamirh!

7 replies, 284 likes

Geoffrey Hinton: This is really nice work

1 replies, 198 likes

Aran Komatsuzaki: Chip Placement with Deep Reinforcement Learning: Comparable or superhuman-level chip placement in 6 hours of training without human experts in the loop using a novel training scheme involving SL and RL.

1 replies, 58 likes

Smerity: Years ago "Device Placement Optimization with RL" opened my eyes to the performance possibilities of ML in replacing simple human heuristics and intuition. Originally RL optimized the use of hardware for training ML. Now RL is optimizing the hardware used for training ML. 🤯

1 replies, 46 likes

Yisong Yue: Outstanding lecture by @Azaliamirh & @annadgoldie on Device & Chip Placement Optimization using RL! Part of @Caltech course on Data-Driven Algorithm Design Video: Slides: Course:

1 replies, 27 likes

Underfox: Researchers have developed a learning-based approach to chip placement which outperforms state-of-the-art baselines and can generate placements that are superior or comparable to human experts on modern accelerators, under 6 hours training.

0 replies, 18 likes

roadrunner01: Chip Placement with Deep Reinforcement Learning pdf: abs:

0 replies, 17 likes

Erik Brynjolfsson: The algorithm placing chips in this simulation reminds me of playing Go. As with Go, deep reinforcement learning can often do better than humans. Kudos to @Azaliamirh, @annadgoldie and @GoogleAI for impressive work! HT: @danielrock #MachineLearning #AI #2MA @CasdeStanford

0 replies, 17 likes

Jeff Dean (@🏡): Nice set of slides and talk by @Azaliamirh and @annadgoldie on our RL for chip placement work described in

0 replies, 17 likes

Anna D Goldie: Great working with you on this, @JeffDean!

0 replies, 11 likes

OGAWA, Tadashi: => "Chip Placement with Deep Reinforcement Learning", Azalia Mirhoseini and Anna Goldie, ..., Jeff Dean, Google, arXiv, Apr 22, 2020 Anna Goldie and Azalia Mirhoseini, ISPD 2020 Jeff Dean, Plenary, ISSCC 2020

1 replies, 8 likes

Naveen @(posedge tech transition) Rao: Chips designing chips! At the very least this could be the start of making the tools for chip design easier to use, thereby increasing access to those designing chips and reducing the price off design

0 replies, 7 likes

OGAWA, Tadashi: => "The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design", Jeff Dean, Google, Plenary, ISSCC 2020 ML for ASIC Chip Placement and Routing Companion paper, Nov 13, 2019 =>

1 replies, 6 likes

Daisuke Okanohara: They solved the chip placement problem by RL, where the netlist is converted by graph NN, and a transferrable representation is learned by the reward prediction task. Their method can generate placement that is better or equal to the one by human experts.

0 replies, 6 likes

Julian Togelius: PCGRL for a non-game

0 replies, 3 likes

Estesis: Chip Placement with Deep Reinforcement Learning Mirhoseini et al.: #MachineLearning #ArtificialIntelligence #ReinforcementLearning

0 replies, 1 likes

Yisong Yue: Learn about how to frame allocation & layout design as deep reinforcement learning problems, pre-train using supervised learning, and generalize for zero- & few-shot learning!

0 replies, 1 likes

Stephen Shankland: Interesting Google AI work on how to lay out circuitry modules optimally when designing a chip. Given that chips have billions of transistors doing more and more types of work, that design work is getting harder and harder.

1 replies, 1 likes

Xavier Geerinck: A super interesting paper has been released utilizing Deep Reinforcement Learning for "Chip Placement"!

0 replies, 1 likes


Found on Apr 23 2020 at

PDF content of a computer science paper: Chip Placement with Deep Reinforcement Learning